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JA21000 Series
Useful Voice with Real-Time Clock (RTC)
Features
Single power supply 2.4V - 5.2V 4-bit ADPCM & 8-bit PCM synthesis. 7K-22KHz max. of playing speed for ADPCM synthesizer 12K-32KHz max. of playing speed for PCM synthesizer Provides 3~340 seconds voice@ S.R.= 6kHz & www..com ADPCM 4-bit Max. of two current type DAC audio outputs One PWM output to direct driving a speaker Programmable 2-channel tone melody generator 16 levels of digital volume control Powerful and easy instructions are provided Built in a high quality speech synthesizer On-chip RC oscillator Power saving STOP & HALT modes I/O State Change wake-up option for all of I/O port Support 32K crystal oscillator share with two pins of PA
General Description
JA21000 is a series of 3 to 340 seconds single chip voice synthesizer IC with RTC which contains a PWM direct drive circuit or AUD output for transistor application. In addition, this chip also provides high sink current port pins, multi external interrupt pins function, and multi oscillator options. JA21000 series offers one of the best cost/performance ratios in the toy or industry for controller. It also supplies high-sink current port pins, multi-external wake-up pins function and multi-oscillator options. The JA21000 series can support 32K crystal oscillator for timer with low operating current. In addition, this JA21000 series family IC leads users into an easy-to use development environment that shorten developer's period and fasten time-to-market. Moreover, fantastic sound effects can be generated by users easily without writing complex programs. This JA21000 series family offers the best cost/performance ratios for toy, consumer, and industry use.
Selection Table
Part No. Voice Cap. (second ) Max. of key numbers Max. of PWM outputs Max. of DAC outputs Part No. Voice Cap. (second ) Max. of key number Max. of PWM outputs Max. of DAC outputs Note JA21003 3 16 1 JA21064 64 32 1 2 JA21007 7 16 1 JA21085 85 32 1 2 JA21014 JA21018 14 18 16 16 1 1 1 JA21128 JA21170 128 170 64 64 1 1 2 2 JA21032 32 32 1 1 JA21256 256 64 1 2 JA21043 43 32 1 1 JA21340 340 64 1 2
The voice capacity is based on sampling rate of 6KHz and 4-bit ADPCM
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Block Diagram
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Pad Assignment
Pin Name DVSS AVSS PA0 - PA3 PA4 - PA7 PB0 - PB7 AVDD, DVDD OSCI I/O -- -- I/O I/O I -- I Internal -- -- NMOS Open Drain CMOS with pull-high CMOS with pull-high -- -- Description Digital negative power supply Analog negative power supply Keyboards scan output in matrix mode. Normal I/O pins in direct mode. For output mode, they are open drain output; For input mode, they are without pull-high resistor. Keyboards scan output in matrix mode. Normal I/O pins in direct mode. For output mode, they are CMOS output; For input mode, they are with pull-high resistor. Keyboards scan input in direct/matrix mode. PB0 - PB3 pins are for all series. PB4 - PB7 pins are for JA21128 -- JA21340 only. Positive power supply. In RC mode, it connects an external oscillator resistor between OSCI and VDD. As well, the pin can be used as an external clock input. Current type output or PWM type output by mask option. For current type output, it must drive an external transistor and only for JA21018 -- JA21340. For PWM type output, it can drive a speaker directly. (8 ohm - 32 ohm) The AUD1 output is provided to JA21018 -- JA21340, and the AUD2 output is provided to JA21064 -- JA21340 only.
PWM (AUD1) PWMB (AUD2)
O
CMOS or Open Drain
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I/O pins and AUD output selection table Part No JA21003 JA21007 PA port PA0 -- PA3 PA0 -- PA3 PB port PB0 -- PB3 PB0 -- PB3 AUD output X X PWM output V V Register (*) R0 -- R6 R0 -- R6 Part No PA port PB port www..com AUD output PWM output Register (*) (*) Note JA21064 PA0 -- PA7 PB0 -- PB3 AUD1, AUD2 V R0 -- R14 JA21085 PA0 -- PA7 PB0 -- PB3 AUD1, AUD2 V R0 -- R14 JA21014 PA0 -- PA3 PB0 -- PB3 X V R0 -- R6 JA21128 PA0 -- PA7 PB0 -- PB7 AUD1, AUD2 V R0 -- R14 JA21018 PA0 -- PA3 PB0 -- PB3 AUD1 V R0 -- R6 JA21170 PA0 -- PA7 PB0 -- PB7 AUD1, AUD2 V R0 -- R14 JA21032 PA0 -- PA7 PB0 -- PB3 AUD1 V R0 -- R14 JA21256 PA0 -- PA7 PB0 -- PB7 AUD1, AUD2 V R0 -- R14 JA21043 PA0 -- PA7 PB0 -- PB3 AUD1 V R0 -- R14 JA21340 PA0 -- PA7 PB0 -- PB7 AUD1, AUD2 V R0 -- R14
Register Available JA21003 ~ JA21018 R0 ~ R6 R0 ~ R2 R0, R3 ~ R6 R0 R1 ~ R6 R0 ~ R6 R0, R5, R6 R0 ~ R4 R0 JA21032 ~ JA21340 R0 ~ R12 R0 ~ R8 R0 ~ R12 R0 ~ R8 R0 ~ R12 R0 ~ R14 R0 ~ R10 R0 ~ R14 R0 ~ R10 Note For JazEASY v2.5
General Using Timer Function Playing PCM Melody Using Timer Function & Playing PCM Melody Using "FR=MTn" General Using Timer Function Playing PCM Melody Using Timer Function & Playing PCM Melody Port A Initial Status
For JazEASY v2.6
JA21003 ~ JA21018 JA21032 ~ JA21340 PA0 ~ PA3 Input-floating Input-floating PA4 ~ PA7 (*) Input-high Input-high PA0 ~ PA3 Output-low Output-low PA4 ~ PA7 (*) Output-low Input-high (*) Note The PA port of JA21003-JA21018 real body, there is only PA0-PA3. Absolute Maximum Rating Symbol VDD~VSS VIN (for input) VOUT (for all outputs) T (operating) T (storage)
Note For JazEASY v2.5 For JazEASY v2.6
Rating VSS -0.5 ~ VDD +0.5 VSS-0.3 < VIN < VDD+0.3 VSS < VOUT < VDD -10 ~ +60 -55 ~ +125
Unit V V V
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Pad Diagram & Pad Location
1. JA21003
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Pad No. 01 02 03 04 05 06 07 08
Pad Name PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3
X(um) 70 70 70 89.1 198.9 308.7 418.5 528.3
Y(um) 535.5 425.7 315.9 70 70 70 70 70
Pad No. 09 10 11 12 13 14 15
Pad Name VSS OSCI VDD VDD PWM VSS PWMB
X(um) 638.1 747.9 857.7 967.5 1207.9 1521.2 1521.2
Y(um) 70 70 70 70 70 69.3 268.0
Chip size : 1592 x 1263 ( m)2 Note The IC substrate should be connect to VSS
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2. JA21007
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Pad No. 01 02 03 04 05 06 07 08
Pad Name PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3
X(um) 70 70 70 89.1 198.9 308.7 418.5 528.3
Y(um) 535.5 425.7 315.9 70 70 70 70 70
Pad No. 09 10 11 12 13 14 15
Pad Name VSS OSCI VDD VDD PWM VSS PWMB
X(um) 638.1 747.9 857.7 967.5 1207.9 1521.2 1521.2
Y(um) 70 70 70 70 70 69.3 268.0
Chip size : 1592 x 1263 ( m)2 Note The IC substrate should be connect to VSS
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3. JA21014
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Pad No. 01 02 03 04 05 06 07 08
Pad Name PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3
X(um) 70 70 70 315.9 425.7 535.5 645.3 755.1
Y(um) 308.7 198.9 89.1 70 70 70 70 70
Pad No. 09 10 11 12 13 14 15
Pad Name VSS OSCI VDD VDD PWM VSS PWMB
X(um) 864.9 974.7 1084.5 1194.3 1462.4 1794.8 1794.8
Y(um) 70 70 70 70 70 69.3 287.2
Chip size : 1865 x 1283 ( m)2 Note The IC substrate should be connect to VSS
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4. JA21018
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Pad No. 01 02 03 04 05 06 07 08
Pad Name PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3
X(um) 70 70 70 315.9 425.7 535.5 645.3 755.1
Y(um) 308.7 198.9 89.1 70 70 70 70 70
Pad No. 09 10 11 12 13 14 15
Pad Name VSS OSCI VDD VDD PWM VSS PWMB
X(um) 864.9 974.7 1084.5 1194.3 1462.4 1794.8 1794.8
Y(um) 70 70 70 70 70 69.3 287.2
Chip size : 1865 x 1283 ( m)2 Note The IC substrate should be connect to VSS
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5. JA21032
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Pad No. 1 2 3 4 5 6 7 8 9 10
Pad Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1
X(um) 70 70 70 70 70 70 70 70 392.2 502.4
Y(um) 869.3 759.1 648.9 538.7 428.5 318.3 208.1 97.9 70.2 70.2
Pad No. 11 12 13 14 15 16 17 18 19
Pad Name PB2 PB3 VSS OSCI VDD VDD PWM VSS PWMB
X(um) 612.6 722.8 833 943.2 1053.4 1163.6 1403.8 1602.5 1801.2
Y(um) 70.2 70.2 70.2 70.2 70.2 70.2 70.2 70.2 70.2
Chip size : 2063 x 2118 ( m)2 Note The IC substrate should be connect to VSS
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6. JA21043
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Pad No. 1 2 3 4 5 6 7 8 9 10
Pad Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1
X(um) 70 70 70 70 70 70 70 70 392.2 502.4
Y(um) 869.3 759.1 648.9 538.7 428.5 318.3 208.1 97.9 70.2 70.2
Pad No. 11 12 13 14 15 16 17 18 19
Pad Name PB2 PB3 VSS OSCI VDD VDD PWM VSS PWMB
X(um) 612.6 722.8 833 943.2 1053.4 1163.6 1403.8 1602.5 1801.2
Y(um) 70.2 70.2 70.2 70.2 70.2 70.2 70.2 70.2 70.2
Chip size : 2063 x 2118 ( m)2 Note The IC substrate should be connect to VSS
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7. JA21064
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Pad No. 1 2 3 4 5 6 7 8 9 10
Pad Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1
X(um) 70 70 70 70 70 70 70 70 392.2 502.4
Y(um) 869.3 759.1 648.9 538.7 428.5 318.3 208.1 97.9 70.2 70.2
Pad No. 11 12 13 14 15 16 17 18 19
Pad Name PB2 PB3 VSS OSCI VDD VDD PWM VSS PWMB
X(um) 612.6 722.8 833 943.2 1053.4 1163.6 1403.8 1602.5 1801.2
Y(um) 70.2 70.2 70.2 70.2 70.2 70.2 70.2 70.2 70.2
Chip size : 2063 x 2118 ( m)2 Note The IC substrate should be connect to VSS
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8. JA21085 JA21085 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pad Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS OSCI VDD VDD PWM VSS PWMB X(um) 70 70 70 70 70 315.9 425.7 535.5 645.3 755.1 864.9 974.7 1084.5 1194.3 1304.1 1413.9 1523.7 1633.5 1743.3 1983.8 1983.8 1983.8 1983.8 Y(um) 528.3 418.5 308.7 198.9 89.1 70 70 70 70 70 70 70 70 70 70 70 70 70 70 71.1 339.2 557.1 775
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Note The IC substrate should be connect to VSS
Chip size : 2054 x 3211 ( m)2
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9. JA21128 JA21128 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pad Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS OSCI VDD VDD PWM VSS PWMB X(um) 70 70 70 70 70 315.9 425.7 535.5 645.3 755.1 864.9 974.7 1084.5 1194.3 1304.1 1413.9 1523.7 1633.5 1743.3 1983.8 1983.8 1983.8 1983.8 Y(um) 528.3 418.5 308.7 198.9 89.1 70 70 70 70 70 70 70 70 70 70 70 70 70 70 71.1 339.2 557.1 775
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Note The IC substrate should be connect to VSS
Chip size : 2054 x 3211 ( m)2
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10. JA21170 JA21170 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pad Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VSS OSCI VDD VDD PWM VSS PWMB X(um) 70 70 70 70 70 315.9 425.7 535.5 645.3 755.1 864.9 974.7 1084.5 1194.3 1304.1 1413.9 1523.7 1633.5 1743.3 1983.8 1983.8 1983.8 1983.8 Y(um) 528.3 418.5 308.7 198.9 89.1 70 70 70 70 70 70 70 70 70 70 70 70 70 70 71.1 339.2 557.1 775
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Note The IC substrate should be connect to VSS
Chip size : 2054 x 3211 ( m)2
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11. JA21256
JA21256 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pad Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VDD VSS LVDET INTB TMR RESB OSCO OSCI VDD PWM VSS X(um) 70 70 70 70 70 70 70 70 70 70 70 70 70 70 335.2 445.4 555.6 665.8 776 886.2 996.4 1106.6 1216.8 1327 1437.2 1547.4 1657.6 2015.9 2015.9 2015.9 2015.9 2015.9 2015.9 2015.9 2015.9 Y(um) 1530.3 1420.1 1309.9 1199.7 1089.5 979.3 869.1 758.9 648.7 538.5 428.3 318.1 207.9 97.7 70 70 70 70 70 70 70 70 70 70 70 70 70 97.7 207.9 318.1 428.3 538.5 667.7 972.9 1190.2
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Note 1. The IC substrate should be connect to VSS 2. The "RESB" pin should be connected to VDD 3. The "TMR" pin should be connected to VDD or VSS
PWMB 2015.9 1407.5 Chip size :2086.1 x5810.15 ( m)2
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12. JA21340
JA21340 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pad Name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VDD VSS LVDET INTB TMR RESB OSCO OSCI VDD PWM VSS X(um) 70 70 70 70 70 70 70 70 70 70 70 70 70 70 335.2 445.4 555.6 665.8 776 886.2 996.4 1106.6 1216.8 1327 1437.2 1547.4 1657.6 2015.9 2015.9 2015.9 2015.9 2015.9 2015.9 2015.9 2015.9 Y(um) 1530.3 1420.1 1309.9 1199.7 1089.5 979.3 869.1 758.9 648.7 538.5 428.3 318.1 207.9 97.7 70 70 70 70 70 70 70 70 70 70 70 70 70 97.7 207.9 318.1 428.3 538.5 667.7 972.9 1190.2
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Note 1. The IC substrate should be connect to VSS 2. The "RESB" pin should be connected to VDD 3. The "TMR" pin should be connected to VDD or VSS
PWMB 2015.9 1407.5 Chip size : 2086.1 x 5810.15 ( m)2
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I/O Port structure
For the PA0~PA3, they are defined as NMOS open drain output only when PAC is set as output mode.
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For the others of the Port A, they can be configured as follows
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Electrical Characteristics
Symbol Parameter VDD 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V Test Condition Condition System HALT, 32768 Crystal Off System HALT, 32768 Crystal On Fsys=4MHz 0 0.7VDD VDD VRES, System 1.6 re-start VOL=0.1VDD 4 VOH=0.9VDD -2 VIL=0V 50 3.6M Rosc=160K Min. 2.4 Typ. Max. 5.2 2 10 1 1.8 8 -4 100 4M 2 0.3VDD VDD 2.0 Unit V uA uA mA V V V mA mA K Hz
VDD Operating Voltage ISTB1 Standby Current ISTB2 Standby Current
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Operating Current (RC OSC) VIL1 Input Low Voltage for I/O VIH1 Input High Voltage for I/O VRES Power reset voltage I/O Sink Current I/O source Current Pull-High Resistance System Clock (RC OSC)
IOL IOH RPH FSYS1
150 4.4M
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Functional Description
The JA21000 series is 2CH programmable voice synthesizer and melody generator. They provide very powerful functions for the toy applications. By way of Jaztek's tools, the users can program the series chips easily. The spec. of voice & melody of JA21000 series are shown as below @VDD=3V 8 bits PCM Fosc 2MHz 4MHz www..com 6MHz 4 bits ADPCM Fosc 2MHz 4MHz 6MHz Melody Item Tempo Beats Octaves Max. of sampling rate 12KHz 22KHz 32KHz Max. of sampling rate 7KHz 14KHz 22KHz Spec. 68~310 beats/min. 1/24~63/24 C1~B1--- C5~B5 Notes R=380K R=160K R=96K Notes
Notes
Output Definition
There are 4 states can be used in output states declaration. They are "X", "H", "L", and "F". The definitions of states are list as follows. State X H L F Definition Don't care, the output pin is set as "input mode" Output High, the output pin is set as logical "Hi" level. Output Low, the output pin is set in logical "Low" level. Output Flash, the output pin is set as "flash" output. It can define as sequential or synchronous mode.
For the "F" state, two output modes can be defined by " FR=Seq/n" and "FR=Syn/n" commands. The " Seq " and " Syn " mean "Sequential" and "Synchronous" modes, respectively. The n represent to flash rate of output is n times/sec(Hz), it can be 1, 2, 4, or 16 Hz. The flash rate also can be defined as " FR=VV1 or VV2" and "FR=MT1 or MT2". For VVx and MTx commands, the output is synchronous mode only. VV1, VV2: The output level follows with the volume output of channel 1 (VV1) or channel 2 (VV2). MT1, MT2: The output level follows with the melody tempo output of channel1 (MT1) or channel2 (MT2).
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Instruction Set
Path commands Poweron Input state name Out state name Path name Tempo=n Vol=n or Vol_1=n Vol_2=n SR=n or SR_1=n www..com SR_2=n DELAY(N ms or N s) TRn?H:pathname TRn?L:pathname FR=Seq/n, Syn/n, VV1, VV2, MT1 or MT2 END n*Sound file [n*Sound file] Ri=PA STOP1 STOP2 Ri=data Ri=Rj Ri(bn)=1 or 0 Ri=Ri+Rj Ri=Rj+data Ri=Rj.AND.data Ri=Rj.OR.data Ri=Rj.XOR.data Ri=SHL(n) Ri=SHR(n) Ri?data:PathName Ri?Rj:PathName Ri(bn)?1:PathName Ri(bn)?0:PathName Ri:[Path1, Path2, Path3,...,Pathn] Ri=Rand(N) Description To set the power on initial To active input state To active output state To execute the specifies path Define the tempo value (n=68-310) Define the AUD1 output volume (n=0-15) Define the AUD2 output volume (n=0-15) Define the channel 1 sample rate (3K-24KHz) Define the channel 2 sample rate (3K-24KHz) To delay N*1 ms or N*1 s (1 ms ~ 65 s) If TRn is logic High, then pathname is executed. If TRn is logic Low, then pathname is executed. Set the output pulse rate to "n" pulses per second sequentially or synchronously. n=1, 2, 4, 16 Enter power down mode. Play the sound file n times. Play the sound file n times. But is continuing execute next path concurrent. Read Port A to Ri Stop the playback of channel 1 sound. Stop the playback of channel 2 sound. Set the content of Ri to be data Set the content of Ri to be Rj Set bit (bn) to be 1 or 0, bn=0-7 Add Ri with Rj to Ri. Add immediate data with Ri to Ri. And immediate data with Rj to Ri. OR immediate data with Rj to Ri. XOR immediate data with Rj to Ri. Shift left of the Ri content n bits; n=1, 2, ..., 7. Shift right of the Ri content n bits; n=1, 2, ..., 7. If Ri=data then PathName is executed. If Ri=Rj then PathName is executed. If Ri.bn is "1" then PathName is executed. If Ri. bn is "0" then Path Name is executed. Path1 is executed when Ri=1; Path2 is executed when Ri=2;
pathn is executed when Ri=n. Get a random code & put it to Ri. The max of random counter is N. (N 255) Initial the timer. If timer is time-up, then Path is executed. Timer(n): PathName n = 1s 32768s or n = 0.1s 3276.8s TimerON Turn on the timer count. TimerOFF Turn off the timer count. "Vol_1=15" is equal "Vol=15". "SR_1=4KHz" is equal "SR=4KHz" The VV represents voice volume. MT means melody tempo. Ri, Rj are working Registers.
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Application Circuit 1 (JA21003~JA21085)
c
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EasyN (N=4, 8, 12, ... ,32) for JA21003 -- JA21085 Key No Key Name Scan Input Easy 4 TR1 -- TR4 PB0 -- PB3 Easy 8 TR1 -- TR8 PB0 -- PB3 Easy12 TR1 -- TR12 PB0 -- PB3 Easy 16 TR1 -- TR16 PB0 -- PB3 Easy 20 TR1 -- TR20 PB0 -- PB3 Easy 24 TR1 -- TR24 PB0 -- PB3 Easy 28 TR1 -- TR28 PB0 -- PB3 Easy 32 TR1 -- TR32 PB0 -- PB3
Scan Output VSS PA0 -- PA1 PA0 -- PA2 PA0 -- PA3 PA0 -- PA4 PA0 -- PA5 PA0 -- PA6 PA0 -- PA7
Output State(I/O pins) PA0(OUT0) -- PA7(OUT7) PA2(OUT2) -- PA7(OUT7) PA3(OUT3) -- PA7(OUT7) PA4(OUT4) -- PA7(OUT7) PA5(OUT5) -- PA7(OUT7) PA6(OUT6) -- PA7(OUT7) PA7(OUT7) X
Note: For JA21003 JA21018 bodies, the max. of Easy N is Easy 16. For JA21032 JA21085 bodies, the max. of Easy N is Easy 32. The AUD1 and AUD2 is shared with PWM and PWMB.
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Application Circuit 2 (JA21128~JA21340)
c
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EasyN (N=8, 16, 24, ... ,64) for JA21128 -- JA21340 Key No Key Name Scan Input Easy 8 TR1 -- TR8 PB0 -- PB7 Easy 16 TR1 -- TR16 PB0 -- PB7 Easy 24 TR1 -- TR24 PB0 -- PB7 Easy 32 TR1 -- TR32 PB0 -- PB7 Easy 40 TR1 -- TR40 PB0 -- PB7 Easy 48 TR1 -- TR48 PB0 -- PB7 Easy 56 TR1 -- TR56 PB0 -- PB7 Easy 64 TR1 -- TR64 PB0 -- PB7 Note: The AUD1 and AUD2 is shared with PWM and PWMB.
Scan Output VSS PA0 -- PA1 PA0 -- PA2 PA0 -- PA3 PA0 -- PA4 PA0 -- PA5 PA0 -- PA6 PA0 -- PA7
Output State PA0(OUT0) -- PA7(OUT7) PA2(OUT2) -- PA7(OUT7) PA3(OUT3) -- PA7(OUT7) PA4(OUT4) -- PA7(OUT7) PA5(OUT5) -- PA7(OUT7) PA6(OUT6) -- PA7(OUT7) PA7(OUT7) X
Preliminary
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JA21000 Series
Application Notes
I. Common key definition v.s. programming
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Example: easy 4 one.wav/ad4 ; #0 input states ; TG1 TG2 TG3 state0: /KEY1 X X state1: X X X paths poweron: state0 end KEY1: state1 1*#0 state0 end
TG4 ........ X X
Example: easy 4 one.wav/ad4 ; #0 input states ; TG1 TG2 TG3 state0: /KEY1 X X state1: /KEY2 X X paths poweron: state0 end KEY1: state1 1*#0 state0 end KEY2:stop1 end
TG4 ........ X X
Preliminary
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JA21000 Series
Example:
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easy 4 one.wav/ad4 ; #0 input states ; TG1 TG2 TG3 state0: /KEY1 X X state1: KEY2/ X X paths poweron: state0 end KEY1: state1 1*#0 KEY1 end KEY2:stop1 end
TG4 ........ X X
Example: easy 4 one.wav/ad4 ; #0 input states ; TG1 TG2 TG3 TG4 ........ state0: /KEY1 X X X state1: X X X X paths poweron: state0 end KEY1: state1 1*#0 TR1?L:KEY1 state0 end
Preliminary
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JA21000 Series
II. 32K Crystal Oscillator Application JA21000 series provide two power saving modes, one is HALT and the other is STOP mode. In HALT mode, the 32K crystal is on and system clock is off. Timer overflow and PX change state can wakeup the system. In HALT mode, 32K crystal offers the Timer count source and the power consumption only takes few uA. This is very useful in long-term timer count application. 32768Hz Crystal oscillator shares with PA table Part No. Description JA21340 PA 6~7 JA21256 PA 6~7 www..com JA21170 PA 6~7 JA21128 PA 6~7 JA21085 PA 6~7 JA21064 PA 6~7 JA21043 PA 6~7 JA21032 PA 6~7 JA21018 PA 2~3 JA21014 PA 2~3 JA21007 PA 2~3 JA21003 PA 2~3 Note The PA n & PA n+1 or 32K crystal mode is selected by code option.
For example, if using JA21032 the application circuit would be
c
Note
The PWM, PWMB and AUD1, AUD2 is shared with the same pins.
Preliminary
TEL 886-3-5770755 FAX 886-3-5770756
24-24
E-mail sales@jaztek.com.tw
Ver. 0.7
Web-site www.jaztek.com.tw

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